Verilog [CPU만들기] Control Block

Mnemonic 어셈블링 명령 

 

 

instruct decoder 코드

module inst_decoder(
    input [7:0] ir_in, 
    output reg nop, outb, outs, add_s, sub_s, and_s, div_s,mul_s, shl,clr_s, psah,shr, load,jz,
                   jmp,jge, mov_ah_cr, mov_ah_dr, mov_tmp_ah,mov_tmp_br,mov_tmp_cr,
                   mov_tmp_dr ,mov_tmp_rr,mov_cr_ah, mov_cr_br,mov_dr_ah ,mov_dr_tmp,
                   mov_dr_br, mov_rr_ah, mov_key_ah, mov_inr_tmp, mov_inr_rr
);

always @(ir_in) begin
                  {nop, outb, outs, add_s, sub_s, and_s, div_s,mul_s, shl,clr_s, psah,shr, load,jz,
                   jmp,jge, mov_ah_cr, mov_ah_dr, mov_tmp_ah,mov_tmp_br,mov_tmp_cr,
                   mov_tmp_dr ,mov_tmp_rr,mov_cr_ah, mov_cr_br,mov_dr_ah ,mov_dr_tmp,
                   mov_dr_br, mov_rr_ah, mov_key_ah, mov_inr_tmp, mov_inr_rr} = 0;
                   
                   case(ir_in)
                    8'h00 : nop = 1;
                    8'h0B : outb = 1;
                    8'h07 : outs = 1;
                    8'h50 : add_s = 1;
                    8'h52 : sub_s = 1;
                    8'h54 : and_s = 1;
                    8'h55 : div_s = 1;
                    8'h51 : mul_s = 1; 
                    8'h15 : shl = 1;
                    8'h10 : clr_s = 1;
                    8'h14 : psah = 1;
                    8'h16 : shr = 1; 
                    8'hD6 : load = 1;
                    8'hD0 : jz = 1;
                    8'hD4 : jmp = 1;
                    8'hD2 : jge = 1;
                    8'h83 : mov_ah_cr = 1;
                    8'h84 : mov_ah_dr = 1;
                    8'h88 : mov_tmp_ah = 1;
                    8'h8A : mov_tmp_br =1;
                    8'h8B : mov_tmp_cr =1;
                    8'h8C : mov_tmp_dr = 1; 
                    8'h8D : mov_tmp_rr = 1;
                    8'h98 : mov_cr_ah = 1;
                    8'h9A : mov_cr_br = 1;
                    8'hA0 : mov_dr_ah = 1; 
                    8'hA1 : mov_dr_tmp = 1;
                    8'hA2 : mov_dr_br = 1;
                    8'hA8 : mov_rr_ah = 1;
                    8'hB0 : mov_key_ah = 1;
                    8'hB9 : mov_inr_tmp = 1;
                    8'hBD : mov_inr_rr = 1;
                    default : nop = 1;
             endcase
end

instruct decoder 테스터벤치 코드

module tb_instr_decoder();

reg [7:0] ir_in;
wire             nop, outb, outs, add_s, sub_s, and_s, div_s,mul_s, shl,clr_s, psah,shr, load,jz,
                   jmp,jge, mov_ah_cr, mov_ah_dr, mov_tmp_ah,mov_tmp_br,mov_tmp_cr,
                   mov_tmp_dr ,mov_tmp_rr,mov_cr_ah, mov_cr_br,mov_dr_ah ,mov_dr_tmp,
                   mov_dr_br, mov_rr_ah, mov_key_ah, mov_inr_tmp, mov_inr_rr;

inst_decoder DUT(
                   ir_in,
                   nop, outb, outs, add_s, sub_s, and_s, div_s,mul_s, shl,clr_s, psah,shr, load,jz,
                   jmp,jge, mov_ah_cr, mov_ah_dr, mov_tmp_ah,mov_tmp_br,mov_tmp_cr,
                   mov_tmp_dr ,mov_tmp_rr,mov_cr_ah, mov_cr_br,mov_dr_ah ,mov_dr_tmp,
                   mov_dr_br, mov_rr_ah, mov_key_ah, mov_inr_tmp, mov_inr_rr
                   );

    initial begin
     ir_in = 0; #100;
     ir_in = 8'h00; #100;
     ir_in = 8'h0B;#100;
     ir_in = 8'h07;#100;
     ir_in = 8'h50;#100;
     ir_in = 8'h52;#100;
     ir_in = 8'h54;#100;
     ir_in = 8'h55;#100;
     ir_in = 8'h51;#100;
     ir_in = 8'h15;#100;
     ir_in = 8'h10; #100;
     ir_in = 8'h14;#100;
     ir_in = 8'h16; #100;
     ir_in = 8'hD6; #100;
     ir_in = 8'hD0; #100;
     ir_in = 8'hD4; #100;
     ir_in = 8'hD2;#100;
     ir_in = 8'h83; #100;
     ir_in = 8'h84; #100;
     ir_in = 8'h88;#100;
     ir_in = 8'h8A; #100;
     ir_in = 8'h8B; #100;
     ir_in = 8'h8C; #100;
     ir_in = 8'h8D;#100;
     ir_in = 8'h98; #100;
     ir_in = 8'h9A; #100;
     ir_in = 8'hA0; #100;
     ir_in = 8'hA1; #100;
     ir_in = 8'hA2; #100;
     ir_in = 8'hA8; #100;
     ir_in = 8'hB0;#100;
     ir_in = 8'hB9; #100;
     ir_in = 8'hBD; #100;
    end
    
endmodule

instruct decoder 시뮬레이션 결과

 

 

Ring counter 코드

 

module ring_counter(
    input clk, reset_p,
    output [11:0] t
    );
    
    reg [11:0] temp = 0;
    
    always @(negedge clk or posedge reset_p) begin
        if(reset_p)temp = 0;
        else if(temp == 0)temp = temp + 1;
        else if (temp == 12'b100_000_000_000)temp = 12'b000_000_000_001;   //숫자 사이에 있는 _는 없는거랑 마찬가지 무시됨
        else temp = temp<<1; //12개중에 1개는 1이 나와야함. 상태머신을 ring counter로 만들어서 clk으로 제어하게 만든것
    end
    
    assign t = temp;
endmodule

 

 

 

Ring counter 시뮬레이션 결과

시뮬레이션 결과

 

control block

 

hs[0], hs[1], ls[0], ls[1] 등을 적당한 출력으로 만드는게 필요하다.

파란 네모 박스는 이번에 진행할 프로세스

 

현재 디코더 ring counter등은 만들었다.